The present invention relates to the design of integrated circuits (ICs), and more specifically, to timing analysis of such circuits.
Generally, ICs have data signals and a clock; the data signal needs to reach a certain node at the correct time vis-a-vis the time when the corresponding clock cycles the device at that node. If the data signal does not arrive in time, the clock is too fast, or alternatively, the data signal is taking too long to propagate (path is too slow).
Coupled noise on a chip is when unwanted energy is transferred from one net (connection between two or more pins) to another net by means of coupled electric/magnetic fields. The net which is receiving the unwanted energy is commonly labeled the victim net, while the net(s) transmitting the unwanted energy are commonly labeled the aggressor net(s). The coupled noise is typically represented as a voltage signal (or multiple signals if there are multiple aggressors) existing on the victim net in addition to the desired/intended signal which was generated by the victim driver. The combination of the victim signal and the aggressor signal(s) represents the total voltage signal on the victim net as seen by the devices connected to the end of the net.
Signals traveling down the aggressor nets at or around the same time as the victim signal can cause unwanted changes in behavior in the devices connected to the victim net, due to the transfer of energy to the victim via the coupled noise. A common example of this pertinent to aspects of the invention is when the coupled noise increases the charge time, and thus the effective delay, of a receiver at the end of the victim net, causing the victim path to fail hardware timing specs (specifications). For example, the coupled noise may increase the charging time of a gate on the data path, causing the data path to be slower, and then producing a condition where the data signal does not arrive on time. The “correct time” mentioned above can also be referred to as the “hardware timing specs” or the “required arrival time” of the data signal. When the slow-down due to noise causes the data to arrive late, specifically later then the required arrival time, this is referred to as a “failure.”
State of the art prediction of coupled noise involves using the relative timing of all aggressor nets with respect to the victim net. In this way, it is possible to determine which aggressor nets do have the potential to affect the victim timing, which aggressor signals will arrive too early/late to affect the victim timing, and which of these aggressor nets can affect the victim simultaneously.
The range of time representing the potential arrival of noise from each aggressor is commonly labeled the aggressor window, while the range of time representing when the victim signal is susceptible to influence from noise, for example when the receiver could be charging, is commonly labeled the victim window.
Consider now out-of-context hierarchical noise analysis. Often in the analysis of large hardware, the hardware is dissected into smaller pieces or subsets of the design. This is done from both an ease of design point of view and an ease of analysis point of view, in order to make things more manageable. Often smaller subsets are nested inside larger subsets in a hierarchical manner.
When analyzing the higher-level subset of the design, the lower level out-of-context or OOC subset will appear to the higher-level subset of the design as a “black box.” When analyzing lower level hierarchical subsets of the design, the original launch time of victim and/or aggressor signals, and therefore the arrival times used to create victim/aggressor windows, may not be known. If the signal on an aggressor started from a point outside, or higher in the hierarchy than, the subset of the design being analyzed, that launch point is outside the scope of the analysis. The estimated/assumed signal arrival times that are used instead are commonly labeled as asserted arrival times.
These asserted arrival times cause uncertainty in the windows, and result in over estimates of the impact of coupled noise in order to safe guard around errors in the asserted arrival time values. The data outside the scope of the current analysis, used to set the asserted arrival times, may not be completely trusted. The design outside the scope of the current analysis may be partially unknown or subject to change, and thus the arrival times may change after the OOC analysis/design has been completed. The current design may be used (copied) in multiple locations across the larger hardware design, so the true arrival times may vary depending on where each use/copy of the current design is located.